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Showing posts with label HPC issue Control. Show all posts
Showing posts with label HPC issue Control. Show all posts

Monday, 12 September 2016

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IBM and NVIDIA Move to Corner the Enterprise Market for AI

A number of coming technologies will undoubtedly change the world as we know it. Two came to light last week while I was trying, and failing, to enjoy an infrequent vacation. One is a power storage technology that has high capacity and doesn’t catch fire or explode like lithium ion batteries. The other, and far more important, is artificial intelligence (AI), which has the potential to change our lives for the better or worse, but dramatically either way.

IBM and NVIDIA Move to Corner the Enterprise Market for AI

An alliance between two of the most powerful companies in this race, IBM and NVIDIA, was announced last week around a small, intelligent, rack-mounted server called the Power System S822LC. This was part of a three-server launch last week and I think the implications are really interesting. NVIDIA is naturally very excited about this.

Let’s explore why this partnership between two powerhouses could be really interesting.

Think

The word that IBM has connected with itself for much of my life is “Think,” and when it announced Watson, it put itself on a path to make that connection a reality. But Watson, as powerful as it is, is an intellectual baby when it comes to where the industry wants to go. Intelligent machines -- computers that can learn, adapt, and then make decisions based on data -- represent the future of computing and, some argue, the future of the human race.



This makes for an impressive potential world impact and the firm, or firms, that get this right first will likely own the next age of computing. IBM, with Watson, got the initial lead, but Watson is expensive to buy and expensive to train.

That’s why this isn’t a one-company effort. It can’t be; it will require a team.

NVIDIA 
Now, while IBM was working on large-scale AI, NVIDIA has been working on packaged intelligence as a technology. Its Drive PX, CX, and DGX-1 platforms are designed to make cars intelligent. However, DGX-1 goes well beyond this in that it forms the basis for the learning that other platforms can use in production. In short, you train the DGX-1 and it trains, at scale, everything else it feeds. This is close, in concept, to being able to manufacture things (initially cars) that come off the line with all of the knowledge they need to operate. If we were talking people, this would be like having a kid that starts out at birth knowing everything you know.

Now we just need to put the parts together.

IBM + NVIDIA
If we combine the two companies, we get the potential for not only a system that is far less expensive to buy but one that is far less expensive to train. The result may potentially be a system that is far smarter than Watson, far more capable than the DGX-1, and able to move both companies to the next tier.

OpenPOWER
The market is currently largely x86, and Intel dominates. Only one non-x86 platform has the potential to address this AI opportunity near term, and that is OpenPOWER, largely because it is backed by IBM and, unlike ARM, it is in production for servers of this class. It is also a technology shared by a variety of vendors, making it more attractive to customers like Google, which is aggressive with AI and particularly favors open systems.

When you combine IBM, NVIDIA and OpenPOWER, you get something unique and potentially very powerful in this race to intelligent computing.

Wrapping Up: Power of the Partnership
In the end, the eventual success of this effort will likely be directly attributable to how well IBM and NVIDIA partner over time. A similar partnership between IBM, Intel and Microsoft created the PC market. If IBM and NVIDIA can do better (that earlier partnership fell apart), then the potential for both firms to own this next technology wave is unmatched. If not, then we’ll just have another story about big firms failing to meet their potential.

For now, IBM and NVIDIA have the inside track, but it’s early in the race. While this new line of servers is a great start, as both companies know, it matters far less who leads a race at the beginning than who leads a race at the end.

Rob Enderle is President and Principal Analyst of the Enderle Group, a forward-looking emerging technology advisory firm.  With over 30 years’ experience in emerging technologies, he has provided regional and global companies with guidance in how to better target customer needs; create new business opportunities; anticipate technology changes; select vendors and products; and present their products in the best possible light. Rob covers the technology industry broadly. Before founding the Enderle Group, Rob was the Senior Research Fellow for Forrester Research and the Giga Information Group, and held senior positions at IBM and ROLM. Follow Rob on Twitter @enderle, on Facebook and on Google+.
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Wednesday, 7 September 2016

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Will IBM’s Power9 Server Chips Pose Competition to Intel’s Server Chips?

IBM’s development of its Power9 architecture has been in the news for some time, and now the company will make it available to other hardware companies by licensing its designs. Power9 chips are scheduled to come in the market in 2H17. Let’s look at some features of the new chips.

IBM’s HPC Power9 Server Chips

Intel’s x86 versus IBM’s Power9
At IDF (Intel Development Forum) 2016, IBM unveiled its Power9 server processors, built on 14nm (nanometer) FinFET (fin-shaped field effect transistor) process technology, just like Intel’s current server processors.

IBM will also integrate Xilinx’s (XLNX) FPGA (field-programmable gate array) technology in its servers, just like Intel is integrating Altera’s FPGA.

Features of Power9
IBM will launch Power9 in two basic designs: a 24 SMT4 processor and a 12 SMT8 processor.

The 24 SMT4 processor will be optimized for the Linux ecosystem and will target web service companies such as Google (GOOG), which need to run across several thousand machines. It will feature four threads.

The 12 SMT8 processor will be optimized for the PowerVM ecosystem and will target larger systems designed for running big data or AI (artificial intelligence) applications. It will feature eight threads.

Both designs will come in two models: the scale-out model will come with two CPU (central processing unit) sockets on the motherboard, and the scale-up model will come with multiple CPU sockets. The Power9 processor will have multiple connectors to attach FPGAs, GPUs (graphics processing units), and ASICs (application-specific integrated circuits).

IBM and Intel eye artificial intelligence
With all this, IBM aims to make Power9 apt for AI, cognitive computing, analytics, visual computing, and hyperscale web serving. Intel is also looking to tap AI and has recently acquired an AI startup called Nervana Systems for this reason. It has also recently developed Xeon Phi processors for deep learning applications.

IBM has changed its strategy in order to pose tough competition to Intel. We’ll look at this strategy in the next part of the series.
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Monday, 22 August 2016

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ARM Announces ARM v8-A with Scalable Vector Extensions: Aiming for HPC and Data Center


Today ARM is announcing an update to their line of architecture license products. With the goal of moving ARM more into the server, the data center, and high-performance computing, the new license add-on tackles a fundamental data center and HPC issue: vector compute. ARM v8-A with Scalable Vector Extensions won’t be part of any ARM microarchitecture license today, but for the semiconductor companies that build their own cores with the instruction set, this could see ARM move up into the HPC markets. Fujitsu is the first public licensee on board, with plans to include ARM v8-A cores with SVE in the Post-K RIKEN supercomputer in 2020.

ARM microarchitecture



Scalable Vector Extensions (SVE) will be a flexible addition to the ISA, and support from 128-bit to 2048-bit. ARM has included the extensions in a way that if included in the hardware, the hardware is scalable: it doesn’t matter if the code being run calls for 128-bit, 512-bit or 2048-bit, the scheduler will arrange the calculations to compensate for the hardware that is available. Thus a 2048-bit code run on a 128-bit SVE core will manage the instructions in such a way to complete the calculation, or a 128-bit code on a 2048-bit core will attempt to improve IPC by bundling 128-bit calculations together. ARM’s purpose here is to move the vector calculation problem away from software and into hardware.
64-bit and 128-bit vectors
This is different to NEON, which works on 64-bit and 128-bit vectors. ARM is soon submitting patches to GCC and LLVM to support the auto-vectorization for VSE, either by directives or detecting applicable command sequences.

Performance metrics performed in ARMs labs show significant speed up for certain data sets already and expect that over time more code paths will be able to take advantage of SVE. ARM is encouraging semiconductor architecture licensees that need fine-grained HPC control to adopt SVE in both hardware and code such that as the nature of the platform adapts over time both sides will see a benefit as the instructions are scalable.
ARMs labs

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